About ASIC DESIGN & MARKETING
Expert Witness Patent Analysis
IC & EDA Marketing
Rapid Systems Prototyping
FPGA & ASIC Implementation
Behavioral HDL & C Design
FPGA & EDA Useful Links
ASIC & EDA BackgroundHome

 

Mapping System-Level Behavioral "C" Designs into Verilog & ASIC/FPGA Hardware

System level designs & algorithms, described using the common "C" language, have been mapped into Register-Transfer-Level (RTL) Verilog for ASIC & FPGA hardware implementation. This new capability accelerates high-level system to hardware design, saving weeks of engineering effort!

Download technical paper on compiling C-Level Designs into Hardware (335K requires Acrobat reader).

 


Located in the heart of Silicon Valley, California
telephone number
contact

© Copyright 1999 - 2004. ASIC DESIGN & MARKETING. All rights reserved.