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Implementing Designs in Field-Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC)

Achieving aggressive design performances with synthesized Verilog/VHDL in an FPGA is still an "art". Let us accelerate your design schedules and teach you proven design techniques!

* Logic Design & EDA Software Usage Assistance

* Design Methodology and FPGA/CPLD Product Selection

* Source of Coaching Expertise by Experienced Engineers

* EDA Software Usage Guidance Personalized to Designer's
Requirements

* Secrets to Obtaining Optimum Performance & Capacity in
FPGA/CPLDs

* Product Seminars & Training Classes

Logic Design Using Gate-Level Schematics & Hardware Description Languages

* Using performance-driven Gate-Level Logic and Memory Primitives to Improve FPGA/CPLD resource Utilization

* Structuring Design Hierarchy and signal Naming Conventions to Improve design documentation and debug

* Coding styles to improve tracing through RTL & Structural Verilog/VHDL Descriptions

* How to use "soft-coded" HDL Intellectual Property Macros (i.e. PCI Interfaces, VGA controllers...)

* How to use FPGA specific "hard-macros" (i.e. PCI interfaces, Counters, Adders, FIFOs, ...)

* Techniques to improve synthesis from Register-Transfer-Level Verilog/VHDL to specific FPGA/CPLD technology libraries using Synopsys, Cadence, & Mentor Graphics software tools

* Impact of Floor-Planning and Relative Location Constraints on Xilinx FPGA resource utilization and interconnect delays

Using performance-driven Gate-Level Logic and Memory Primitives to Improve FPGA/CPLD resource Utilization

* Let us teach your design team proven techniques to achieve the optimum implementation of your design using Application Specific Integrated Circuit, Field Programmable Gate Array, and Complex Programmable Logic Device products. This "coaching" approach achieves the best cost performance results, since your engineering staff understands the desired function and then has the capability to make future modifications.

* Achieving reasonable performances in FPGAs is still an "art", requiring knowledge of IC architecture, preferred HDL coding styles, synthesis control parameters/constraints, and past experience.

Design Verification and Test

* Digital Signal Simulation and Creating Test Benches

* Design for Test (BIST, JTAG, and simple scan)

* Static Timing Analysis (analysis of critical paths & maximum clock frequencies)


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