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Field-Programmable Gate Arrays (FPGA) Technologies

Achieving aggressive design performances with synthesized Verilog/VHDL in an FPGA is still an "art". Let us accelerate
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SRAM Re-Programmable FPGAs with software configuration file (1 to 250 K gates, operating with clocks generally < 100MHz), Coarse-grain "LookUpTable" logic & memory, plus dedicated SRAM blocks

Xilinx: VIRTEX and XC4000 series

Altera: APEX and FLEX EPF8K, 10K, & 20K series

One-Time-Programmable FPGAs using anti-fuse technology (1 to 50 K gates, operating with clocks generally < 100 MHz), Fine-grain "gate logic" modules

Actel: 40MX and ACT series

Re-Programmable FPGAs using FLASH technology (1 to 50 K gates, operating with clocks generally < 100 MHz), Fine-grain "sea-of-modules"

Actel: SX series

Re-Programmable CPLDs using EPROM & FLASH technology (1 to 25 K gates, operating with clocks generally <100 MHz), Matrix of "sum-of-product" arrays with programmable macrocell outputs connected to global signals

Altera MAX EPF7000 & 9000 series

Xilinx: XC9500 series

Lattice ispLSI series


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