Application Specific Hardware Emulation
& ASIC Prototyping using multiple FPGAs
Complex "System-On-Chip" HDL designs using various
Intellectual Property building blocks can be synthesized for implementation
into reconfigurable FPGAs with capacities up to 200,000 gates.
(Capacities up to 1,000,000 gates are projected in the very near
Alternatively, the design can
be partitioned into multiple FPGAs to simplify design iteration.
By interconnecting these FPGAs on a custom Printed Circuit board,
the system can operate with 25-66 MHz clock frequencies, more
than 20x faster than conventional Quickturn Hardware Emulators.
Although the maximum FPGA clock frequencies are less than that
possible with submicron ASICs, the PC-compatible clock frequency
eliminates engineering complex buffer circuits required by slow
clock commercial Hardware Emulators.
Synthesis of Verilog (RTL) hierarchical
modules and partitioning into multiple FPGAs based on input/output
signal constraints and logic capacities is an "art",
where experience improves the results. Performances achieved with
automated partitioning software are usually not adequate for the
clock frequencies desired.
Hardware emulation using custom
Printed Circuit Boards with multiple FPGA and standard ICs achieves
higher speed operation than general purpose commercial products.
The expensive commercial emulator products offer extensive signal
probing capability to analyze logic functionality; however, the
large physical size of this equipment and slow 1 MHz clock frequency
limit their portability.
In some designs, multiple clocks
with frequencies up to 100 MHz are possible.
SRAM based FPGAs from Xilinx,
Altera, or Lucent are easily re-configured to incorporate design
changes (incremental FPGA download) which expedites system software
Re-Configurable Processing Unit
(RPU) H.O.T. Works products from Virtual
Computer Corporation also accelerates cpu intensive computing
with Xilinx PCI-compliant development system.
ASIC Design & Marketing can
create multiple low-cost re-configurable prototypes for system
engineers to verify ASIC functionality and accelerate system development